Positive Development of Train Ultraspeed Protection Technology on Chinese Railways 我国铁路应积极发展列车超速防护技术
This paper introduces a new structure of numeral multilier: using one-level logic gate structure to realize array numeral multiplier, and using cmos technology to realize 8 × 8 ultraspeed array numeral multiplier with a new structure. 本文介绍了一种新的数码乘法器结构:采用一级逻辑门结构实现阵列式数码乘法器,并采用CMOS工艺技术实现新结构的8×8位超高速阵列式数码乘法器。
In addition, the autor describes the imported French U-T ultraspeed protection system has encountered some problems in application on Chinese railways. 对引进的法国U-T超速防护系统在我国铁路运用中遇到的一些问题作了阐述。